This application claims the priority of Korean Patent Application No. 2003-26392, filed on Apr. 25, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to an energy recovery circuit of a plasma display panel and a plasma display panel driving apparatus including the same, and more particularly, to an energy recovery circuit of a plasma display panel, which recovers and supplies charging/discharging energies by operating controlling switches according to charging/discharging operations of a panel capacitor to reduce stress on the controlling switches using a transformer, and a plasma display panel driving apparatus including the energy recovery circuit.
2. Description of the Related Art
FIG. 1 is an inner perspective view of a structure of a plasma display panel in a conventional three-electrodes surface discharging type.
Referring to FIG. 1, address electrode lines AR1, AG1, . . . , AGm, ABm, dielectric layers 11 and 15, Y electrode lines Y1, . . . , Yn, X electrode lines X1, . . . , Xn, a phosphor layer 16, a barrier rib 17, and a magnesium monoxide layer 12 as a passivation layer are disposed between front and rear glass substrates 10 and 13 of a surface discharging plasma display panel 1.
U.S. Pat. No. 5,541,618 discloses an address-display separated driving method which is mainly used as a driving method of the plasma display panel having above structure.
FIG. 2 is a block diagram of a driving apparatus for the plasma display panel shown in FIG. 1.
Referring to FIG. 2, the driving apparatus of the plasma display panel 1 includes an image processing unit 26, a controlling unit 22, an address driving unit 23, X-driving unit 24, and Y-driving unit 25. The image processing unit 26 converts an external analog image signal into a digital signal to generate internal image signals such as image data of red (R), green (G), and blue (B) colors respectively having 8 bits, a clock signal, and vertical and horizontal synchronizing signals. The controlling unit 22 generates driving control signals (SA, SY, SX) according to the internal image signals from the image processing unit 26. The address driving unit 23 processes the address signal SA among the driving control signals SA, SY, SX from the controlling unit 22 to generate a display data signal, and applies the generated display data signal to address electrode lines. The X-driving unit 24 processes X-driving signal SX among the driving control signals SA, SY, SX from the controlling unit 22, and applies the X-driving signal to X-electrode lines. The Y-driving unit 25 processes Y-driving control signal SY among the driving control signals SA, SY, SX from the controlling unit 22, and applies the Y-driving control signal SY to Y-electrode lines.
FIG. 3 is a timing view showing driving signals applied to the panel shown in FIG. 1 on unit sub-field by the address-display separated driving method.
In FIG. 3, reference numerals SAR1, . . . , ABm denote driving signals applied to respective address electrode lines (AR1, AG1, . . . , AGm, ABm in FIG. 1), SX1, . . . , xn denote driving signals applied to the X-electrode lines (X1, . . . , Xn in FIG. 1), and SY1, . . . , Yn denote driving signals applied to the Y-electrode lines (Y1, . . . , Yn in FIG. 1).
Referring to FIG. 3, in a reset period (PR) of the unit sub-field (SF), voltages applied to the X-electrode lines X1, . . . , Xn, rise continuously from ground voltage to second voltage (VS), for example, to 155 V. Here, ground voltages VG are applied to the Y-electrode lines Y1, . . . , Yn and the address electrode lines AR1, . . . , ABm.
Then, voltages applied to the Y-electrode lines Y1, . . . ,Yn rise continuously from the second voltage VS, for example, 155V to the highest voltage (VSET+VS) which is higher than the second voltage VS as much as third voltage (VSET), for example, to 355V. Here, the ground voltages VG are applied to the X-electrode lines X1, . . . , Xn and the address electrode lines AR1, . . . , ABm.
Next, in a status where the voltages applied to the X-electrode lines X1, . . . , Xn are maintained to be the second voltages VS, the voltages applied to the Y-electrode lines Y1, . . . , Yn are descended from the second voltage VS to the ground voltage VG continuously. Here, the ground voltage VG are applied to the address electrode lines AR1, . . . , ABm.
Accordingly, in a next address period (PA), the display data signals are applied to the address electrode lines and scan signals of ground voltages are sequentially applied to the Y-electrode lines Y1, . . . , Yn which are biased to be fourth voltages (VSCAN) lower than the second voltage VS, and thereby performing smooth addressing operations. The display data signals applied to respective address electrode lines AR1, . . . , ABm are applied with address voltage (VA) of straight polarity in a case where a discharge cell is selected, or applied with ground voltages (VG). Here, the second voltages VS are applied to the X-electrode lines X1, . . . , Xn for performing the addressing operation more accurately and effectively.
In a next sustain period (PS), display sustain pulses of second voltages VS are alternatively applied to all Y-electrode lines Y1, . . . , Yn and to the X-electrode lines X1, . . . , Xn to generate a discharge for maintaining the display on the discharging cells in which wall charges are formed in the corresponding address period (PA).
In the plasma display panel, a voltage higher than discharge starting voltage of the discharged gas should be alternately applied between the sustain electrodes (X electrode and Y electrode) in the discharged cell in driving.
Therefore, in order to apply a positive (+) high voltage and a ground voltage (VG) alternately between the sustain electrodes when the plasma display panel is operating, the panel capacitor should be changed and discharged. Here, the panel capacitor consumes a lot of reactive power in the charging/discharging operations, and a size of the panel capacitor increases in proportion to that of the display panel, thus increasing the power consumption.
To solve the above problem, U.S. Pat. No. 4,866,349 discloses an energy is recovery apparatus for reducing power loss in the charging/discharging operations of the panel capacitor.
FIG. 4 is a circuit diagram of a typical energy recovery apparatus using an external capacitor.
Referring to FIG. 4, the general energy recovery circuit 30 includes an inductor (L1) forming an LC resonance circuit with the panel capacitor (Cp) of the display panel. The energy recovery circuit 30 recovers the energy lost when the panel capacitor Cp is discharged through the inductor L1 and temporarily stores the energy, and uses the stored electric current energy in next charging operation of the panel capacitor Cp. This reduces the reactive power in driving the plasma display panel.
The above circuit is included in the conventional energy recovery apparatus using an external capacitor. The energy recovery apparatus further includes a first energy recovery unit 30 and a second energy recovery unit 40 for maintaining the plasma display panel with the sustain voltage Vs, and for recovering the energy lost in the discharging operation of the panel capacitor Cp to provide the panel capacitor Cp with the retrieved energy in the next charging operation. The first and second energy recovery units 30 and 40 are symmetrically configured as interposing the panel capacitor Cp therebetween.
Also, the first and second energy recovery units 30 and 40 are alternately operated so that the voltages (Vp) on both ends of the panel capacitor Cp change respectively to the anode (+) and the cathode (−) in the charging/discharging operations of the panel capacitor Cp.
In FIG. 4, the first energy recovery unit 30 includes a controlling switch S1 for supplying the sustain voltage VS to the panel capacitor Cp in the sustain operation of the display panel, the inductor L1 resonated in the charging/discharging operations of the panel capacitor Cp, one-way diodes D15 and D16 to prevent reversal of the resonance current, an external capacitor C1 for storing the energy recovered when the inductor L1 and the panel capacitor Cp are resonated, and controlling switches S11 and S12 connected between the panel capacitor Cp and the external capacitor C1 for switching the energy recovery path.
FIG. 5 is a waveform diagram showing waveforms according to switching operations of respective controlling switches in the energy recovery apparatus shown in FIG. 4.
Referring to FIG. 5, waveforms of voltages on the both ends of the panel capacitor Cp and waveforms of the current flowing on the inductor L1 according to the switching operation of the respective controlling switches in the general energy recovery apparatus are shown as I and II in FIG. 5.
First, the conventional energy recovery apparatus is to reduce the loss of electric power due to the reactive power generated when the charged panel capacitor Cp is discharged after the system power is applied and the plasma display panel is sustained. Also, the energy transfer in the charging/discharging operations of the panel capacitor Cp is made through the resonance operation between the panel capacitor Cp and the inductor L1.
Also, the energy recovery apparatus operates in four sections (T1˜T4) as shown in FIG. 5. The second energy recovery unit 40 operates in the same manner as the first energy recovery unit 30. Following is described how the energy recovery unit operates.
The charged energy of the panel capacitor Cp is stored in the external capacitor C1 through the resonance between the inductor L1 and the panel capacitor Cp.
The resonance current i1 of the inductor L1 and the panel capacitor Cp is formed from the external capacitor C1 included in the first energy recovery unit 30, and voltages Vp on both ends of the panel capacitor Cp rise to the sustain voltage VS by the resonance current i1. Here, the controlling switch S11 is turned on so as to provide the current path (section T1).
Next, the controlling switch S1 is turned on to sustain the plasma display panel, and the sustain voltages are continually applied as the voltages Vp on both ends of the panel capacitor Cp (section T2).
After sustaining the display panel, the inductor L1 and the panel capacitor Cp are resonated in the discharging operation of the panel capacitor Cp so that the charged energy of the panel capacitor Cp is recovered in the outer capacitor C1 of the first energy recovery unit 30. Here, the controlling switch S12 is turned on so as to provide the current path (section T3).
Next, the controlling switch S2 is turned on, and the voltages Vp on both ends of the panel capacitor Cp are maintained at zero electric potential (section T4).
Here, the both ends voltages Vp of the panel capacitor Cp rises from the external capacitor C1 that is charged with the voltage corresponding to half of the sustain voltage Vs to the sustain voltage Vs by the resonance operation of the inductor L1 and the panel capacitor Cp. However, a voltage is actually lost as much as Δ due to a line resistance and other parasitic resistance of devices in the circuit. This lowers energy recovery efficiency and panel driving features due to the discharge before sustaining the display panel.
Therefore, the sustain voltage cannot rise to the desired voltage Vs or cannot be lowered to the ground voltage 0V. When the sustaining operation is performed in this status, the switches for applying and discharging the sustain voltage perform hard-switching operations, creating problems of electromagnetic interference (EMI).
Also, in the conventional energy recovery apparatus, the rising or descending time of the panel voltage is long, thus generating the panel discharge in the energy recovery section. Here, the dropped panel voltage causes a hard-switching operation in applying the sustain voltage at the voltage much less than the sustain voltage. This increases a surge current and stresses the switch.